The present invention relates to a write method for a semiconductor memory cell and particularly an SRAM (Static Random Access Memory) memory cell, and a semiconductor memory circuit device.
FIG. 7 shows the arrangement of a 1-bit SRAM memory cell as a semiconductor memory circuit device related to the present invention. Two inverters IN1 and IN2 are cross-coupled to each other. The two terminals of a switching transistor T1 are connected between one connection node N1 and a bit line BL. The two terminals of a switching transistor T2 are connected between the other connection node N2 and a bit line /BL. The gates of the transistors T1 and T2 are connected to word lines WL. The inverters IN1 and IN2 are respectively connected to a power supply terminal PL and a ground terminal GL.
A write operation in this device will be explained with reference to a timing chart in FIG. 8. The following description is related to the case of writing logically inverted data (the potential of the node N1 is the ground potential, and that of the node N2 is the power supply potential) for data (the potential of the node N1 is the power supply potential, and that of the node N2 is the ground potential) stored in an SRAM memory cell at that time.
Write procedures are classified into Method 1 in which data is input to the bit line simultaneously when or after raising the potential of the word line, as shown in FIG. 8(a), and Method 2 in which the potential of the word line is raised after inputting data to the bit line, as shown in FIG. 8(b).
(Method 1)
Up to time t1, the bit lines BL and /BL are kept precharged to the reference potential. The power supply line PL is at the power supply potential, and the ground line GL is at the ground potential. In this case, the reference potential is the power supply potential, but may be the ground potential or intermediate potential. In this stage, of the two nodes N1 and N2 cross-coupling the inverters IN1 and IN2 in the above-described manner, the node N1 holds the power supply potential, and the node N2 is at the ground potential.
For a time interval from time t1 to time t2, the potential of the word line WL rises to turn on the switching transistors T1 and T2.
At the same time as or after time t1, the potential of the bit line BL is changed to the ground potential (logic "O"), whereas that of the bit line /BL to the power supply potential (logic "1"). Data is written via the transistors T1 and T2 in the ON state, and the potentials of the nodes N1 and N2 respectively change to the ground potential and the power supply potential. As a result, the data is written in the SRAM memory cell.
For a time interval from time t3 to time t4, the potential of the word line WL is decreased to the ground potential to turn off the transistors T1 and T2. From time t4, the bit lines BL and /BL are precharged to the reference potential.
(Method 2)
Similar to Method 1, up to time t1, the bit lines BL and /BL are kept precharged to the reference potential. The power supply line PL is at the power supply potential, and the ground line GL is at the ground potential. The node N1 is at the power supply potential, and the node N2 is at the ground potential.
From time t1, the bit lines BL and /BL are respectively changed to the ground potential and the power supply potential. For a time interval from time t2 to time t3 after the bit lines BL and /BL respectively reach the corresponding potentials, the potential of the word line WL is raised to turn on the transistors T1 and T2. Then, data is written, and the potentials of the nodes N1 and N2 respectively change to the power supply potential and the ground potential.
For a time interval from time t4 to time t5, the potential of the word line WL is decreased to turn off the transistors T1 and T2. From time t5, the bit lines BL and /BL are precharged to the reference potential.
This device has the following problems. As described above, in writing data, the bit lines BL and /BL must have a potential difference between the power supply potential and the ground potential. Since the load of the bit line is very heavy, a long time is required to drive the bit lines BL and /BL so as to attain a potential difference between the power supply potential and the ground potential, increasing the power consumption. During a write, the current amount flowing from the power supply terminal to the ground terminal, and the current amount flowing from the bit line to the ground terminal are large, increasing the power consumption. Also in precharging the bit line upon a write, a long time is required to increase the power consumption because the potential difference between the bit lines BL and /BL is large.